Electronic feedback controlled time-division multiplier and/or divider

ABSTRACT

An electronic system for simultaneously multiplying and dividing analog signals which comprises a closed loop circuit in which the division is accomplished by introducing the dividend signal into the main signal translating portion of the circuit and the divisor signal into the feedback portion of the circuit. The output signal of this closed loop circuit has a varying duty cycle which is proportional to the quotient of these signals, and this quotient is multiplied by a third signal in an electronic switch which is connected to the output of the above closed loop circuit.

United States Patent 1191 11 3,737,040 Pao et al. [4 1 June 5, 1973 541ELECTRONIC FEEDBACK 2,966,306 12/1960 lsabeau ..235/194 CONTROLLEDTIME-DIVISION 3,482,451) 9; 1969 gonnogy .....235/ 194 X 3,4 ,4 l 1970rowe ..235/l94 MULTIPLIER AND/OR DIVIDER 3,610,910 10/1971 Udall..235/l94 [75] Inventors: Robert K. C. Pan, Charlotte, N.C.;

Willis R. Burgener, St. Louis, Mo. Primary Examiner-J0seph F. Ruggiero[7 3] Assignee: Monsanto Company, St. Louis, Mo. Atmmey Hal-Old Patton[22] Filed: Dec. 29, 1971 [57] ABSTRACT [21] Appl. No.: 213,482 Anelectronic system for simultaneously multiplying and dividing analogsignals which comprises a closed loop circuit in which the division isaccomplished by "235/195 23? introducing the dividend signal into themain signal [58] Fie'ld 196 translating portion of the circuit and thedivisor signal 307/229 into the feedback portion of the circuit. Theoutput 328/166 signal of this closed loop circuit has a varying dutycycle which is proportional to the quotient of these signals, and thisquotient is multiplied by a third signal [56] References Cited in anelectronic switch which is connected to the out- UNTTED STATES PATENTSput of the above closed loop circuit.

3,569,688 3/1971 Brendle ..235/ 194 21 Claims, 2 Drawing Figures ERRORVOLTAGE GENERATION VOLTAGE To DUTY l8 l4 CYCLE CONVERTER A- I I I9COMPENSATING en I l 1 Id 24 NETWORKS COMPARATOR i 5 I I /\N\/\ 5 I lTRIANGLE l wAvE GENERATOR I j l k -d-b I5 5 DUTY CYCLE-To- |TIM-U222VOLTAGE CONVERTER E as 28 fCl INTEGRATOR ELECTRONIC OUTPUT SWITCH LOWPASS DRIVER FILTER STAGE ELECTRONIC FEEDBACK CONTROLLED TIME-DIVISIONMULTIPLIER AND/OR DIVIDER FIELD OF THE INVENTION This invention relatesgenerally to electronic computing circuitry and more particularly toelectronic circuitry capable of simultaneously multiplying and dividingthree separate input variables.

BACKGROUND Various types of time division multipliers and dividers havebeen employed in the prior art, and these electronic circuits areoperable to generate an output voltage which is equal to some gainconstant, k, times ac/b where a and c are the two independent inputvariables to be multiplied and b is the third independent input variablewhich is the divisor. For example, one type of known prior art circuitfor performing the above algebraic function utilizes an operationalamplifier to which is connected a first input variable a, and a separatemultiplier stage is connected in the operational amplifiers feedbackloop for receiving the divisor input variable b. When properly connectedand biased, this closedloop feedback system is operative to generate anoutput voltage which is proportional to the quantity a/b. The output ofthe operational amplifier may then be further connected to a secondmultiplier stage which is connectable to receive a third input variablec, so that the output of this second multiplier stage is an outputvoltage proportional to the quantity ac/b.

For a high degree of accuracy, the above type of prior artmultiplier-divider system commonly utilizes a time division (pulse widthmodulation) technique which requires a precisely shaped clock waveform,such as a triangular waveform, to drive one or both of the abovemultiplier stages at some preselected clock frequency. While these priorart systems have operated satisfactorily in the past as long as theclock generators therefor produce this waveform or waveforms of aprecise shape, these systems are subject to error where the shape of theabove clock or time base generator waveform varies slightly from aprecise chosen waveform shape. For example, this clock signal may beapplied to one of two inputs of a differential comparator amplifierwithin the system and the independent variable signal voltage may beapplied to the other input of the comparator amplifier and chopped ormodulated in accordance with the precise shape of the periodic clocksignal. When the shape of this clock signal varies slightly from itsdesired shape, then the switching threshold of the comparator amplifierwill also vary as a result of the latter and thereby introduce errorinto the multiplying or dividing function of the system.

THE INVENTION The general purpose of this invention is to provide a newand useful time division electronic multiplier and divider system havingall of the advantages of the aforedescribed and other prior art timedivision multipliers and dividers, while at the same time providing trueand accurate division and multiplication of three separate inputvariables independent of the precise shape of the waveform of thedriving clock signal. To attain this, the multiplier-divider accordingto the present invention has been constructed to include a duty cyclecontrolled, closed-loop circuit servo system wherein a first analoginput signal a is applied to the main or primary signal translatingportion of the servo loop and therein compared to a feedback signal V, Asecond analog divisor signal b is applied to the feedback circuit i.e.feedback loop of the system, and therein modulated by a variable dutycycle output signal at the output of the main signal translating portionto thereby produce the above feedback signal V The main signaltranslating portion of the system includes means for generating an errorsignal which is a function of the difference between the feedbacksignal, V,, and the a signal, and this error signal is modulated in avoltage-to-duty cycle converter to produce the variable duty cycleoutput signal proportional to a/b. This signal continuously forces V,toward a, so that the a/b output signal is independent of the shape ofthe clock (modulating) signal used to chop the error voltage. This errorvoltage is the integral of the comparison difference signal of V, and a,so that the system is provided with a good reset response, andadditionally includes a desirable high DC. gain and a high frequencystability. The a/b variable duty cycle output voltage may be utilized tomodulate a third input signal variable 0. This modulated signal Vd isproportional to (a.c)/b and is then filtered and amplified for driving afinal control element or the like in a process control system.

Accordingly, an object of the present invention is to provide a new andimproved electronic multiplierdivider system for accurately generatingthe product and quotient of three independent input variables.

Another object of the invention is to provide a system of the typedescribed whose error-free operation is independent of the precise shapeof the waveform of the main clock generator of the system.

Another object of this invention is to provide new and useful electronicmultiplier/divider circuitry of the type described which is particularlyadaptable for use in the field of process control and which has a highstatic accuracy and a stable closed-loop response.

A further object of this invention is to provide a new and improvedmultiplier/divider system of the type described which may be simply andeasily constructed using individually known, commercially available andrelatively inexpensive operational amplifiers and solidstate electronicswitches.

These and other objects and features of this invention will becomeapparent in the following description thereof.

DRAWINGS FIG. 1 is a functional block diagram of a preferred embodimentof the electronic computing system according to the present invention,and

FIG. 2 is adetailed schematic diagram of the system shown in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a firstinput signal a is received on input terminal 10 and is processed througha comparator l2 and through compensating networks 14 where it controlsthe generation of a compensates error voltage e on line 16 and at theinput of the voltage-toduty cycle converter stage 18. Stages 12 and 14provide a means for generating the error signal e, and as will bedescribed in detail below, the networks 14 provide integral reset actionwhich continuously forces the output difference signal e of thecomparator 12 to zero during the generation of the variableduty cycleoutput signal 22. The converter stage 18 includes an operationalamplifier comparator 19 which is driven by a clock pulse trianglewaveform generator 20. The output signal of the comparator 19 has a dutycycle, d, is proportional to the analog value of 2 which determines theswitching threshold of the comparator 19. Thus, comparator 19 andgenerator 20 provide a voltage-toduty cycle converter functioning asmeans for receiving and modulating the error signal e The stagesdescribed thus far are within the main or primary signal translatingportion 13 of the system.

The variable duty-cycle signal 22 at the output terminal 24 of the stage18 is fed directly into a duty-cycleto-voltage converter 26 in thefeedback portion of the system, and the converter 26 is alsosimultaneously driven by a second independent divisor voltage b togenerate a feedback signal V,. The feedback voltage, V which is returnedto the comparator 12, may be expressed as where k, is the gain constantfor the converter stage 26. When this servo loop is operating in itsnull condition, then the input signal a V,, the error difference signale at the output of comparator 12 equals zero, and the compensated errorsignal e is constant. However, when e is any value other than zero, thenthe networks 14 continuously generate, by reset action, an integralerror signal 2,, which, by closed loop feedback control, forces V,toward a and thereby produces the signal 22 proportional to a/b, andindependent of the shape of the triangular waveform of generator 20.

The chopped signal 22 of duty cycle d on line 28 is provided as oneinput to an electronic switch 30, such as a field-effect transistor(PET), and this switch 30 is also simultaneously driven by a thirdindependent variable input voltage 0 which is chopped or modulated inthe switch 30 at the frequency of the variable dutycyele signal 22 online 28. Thus, the output voltage V of the electronic switch 30 may beexpressed as where k; is equal to the gain constants associated with theincoming signal c. This voltage V,, at the output of switch 30 isfiltered and integrated in the integrator and filter stage 32 and thenamplified in the current amplifier stage 34 which includes both currentand voltage outputs as shown in FIG. 2.

The multiplying and dividing functions accomplished by the presentinvention may be explained as follows with reference to FIG. 1, and thismultiplying and dividing action will also be further discussed belowwith reference to FIG. 2.

For a null condition and with the error signal e=0, the incoming signala is equal to the feedback voltage, V,, so that Therefore, the variableduty-cycle signal 22 which is applied to the electronic'switch 30 may beexpressed as d m/mow) Since the variable duty-cycle signal 22 on line 28modulates the input signal voltage c in the electronic switch 30, theoutput voltage V of the electronic switch 30 may, by combining equations(2) and (4) above, be expressed as Thus, the output voltage, V0, at theoutput of stage 34 may be expressed as where k is the gain constantassociated with stages 32 and 34. Therefore, from the equation 6 above,it can be seen that the output voltage, V0, is independent of theprecise shape of the triangular waveform at the output of the triangularwave generator 20 which drives the operational amplifier comparator 19,and this is an extremely significant feature of the present invention.

Referring now to FIG. 2 in detail, there are shown the a, b and c inputterminals 36, 38, and 40, respectively, and the three input signals a, band c are connected through their respective series input resistors 42,44, and 46 to the summing junctions 48, 50, and 52 of the threeisolation operational amplifiers 54, 56, and 58. A plurality of negativeD.C. offset voltages V,, V and V are applied respectively to inputterminals 60, 62, and 64 as shown, and these offset range settingvoltages are connected through series resistors 66, 68 and 70 to theabove identified summing junctions 48, 50 and 52. The isolationoperational amplifier 54 has its inverting input terminal groundedthrough resistor 74 and also has a feedback resistor 72 connected asshown between the output and input of operational amplifier. The analogsignal a is processed through the unity gain operational amplifier 54and through the series resistor 76 into the summing junction 10 of thecomparator or deviation operational amplifier 12. The isolationoperational amplifiers 56 and 58 are further connected with feed-backresistors 57 and 59, respectively and are also connected to drive theFET switches 30 and 96 as will be described further below.

The op amp comparator 12 has a feedback resistor 78 connected betweenits output node and the summing junction 10, and the noninverting input82 of the comparator operational amplifier 12 is grounded throughresistor 80. The operational amplifier input 82 is also connected toreceive the feedback signal designated V, which will be described inmore detail below.

The output signal of the comparator operational amplifier 12 is an errorsignal 2 which is the difference between the analog input signal a andthe servo loop feedback signal V,. The error signal e is coupled throughthe compensating network 14 which comprises an integrator and low passfilter constructed using an operational amplifier 84 having a feedbackcapacitor 86 connected between the output thereof and the invertinginput 88 of operational amplifier 84. The inverting input 88 ofoperational amplifier 84 is grounded as shown through resistor 90, andthe integrator and low pass filter compensating network 14 provides adesired high DC. gain and a high frequency stability for the servosystem described above. Furthermore, this network 14 continuouslyintegrates the difference error signal e to generate e and thus providea highly responsive reset action which continuously forces V, to equala.

The compensated (integrated and filtered) error signal e, at the outputnode 16 of the operational amplifier 84 is connected to the noninvertinginput terminal of comparator 19 in the voltage-to-duty-cycle converterstage 18. The inverting input terminal of comparator 19 is connected tothe output of a triangular wave generator 20 which provides the drivingtriangular waveform 21 for the comparator 19. When the triangularwaveform 21 rises and falls above and below the analog level of thecompensated analog signal e applied to the noninverting input of thecomparator 19, the output of comparator 19 is switched between twodiscrete D.C. levels; and the duty cycle, d, of this rectangular waveoutput signal at the output 24 of the comparator 19 is proportional tothe analog signal level of the compensated error signal e This variableduty cycle signal 22 is independent of the exact shape of waveform 21and is applied via feedback line 28 simultaneously to the cathodes of apair of steering diodes 92 and 94, respectively. For example, if theslope of the triangular wave clock signal 21 should vary slightly from apreselected value, then momentarily the duty cycle, d, of feedbacksignal 22 will change as a result of operational amplifier 19 nowswitching at a different point in time within the period of the clocksignal. This variation will momentarily produce a change in the level ofV,, and this change in V, will in turn produce a corresponding change ine This latter change compensates for the slope variation in thetriangular waveform 21 and forces the duty cycle d to return to thevalue which causes V, to equal a. Thus the duty cycle d varies only inaccordance with the value of a/b and remains independent of the preciseslope of the triangular clock waveform 21. Thus, this extremelyimportant feature of the present invention substantially reduces thetolerance requirements for the circuit design of the triangular waveformgenerator 22, and this clock generator 20 is not required to provide anoutput triangular waveform 21 having a constant shape at all times. Thatis, the clock waveform is not required to have either a constant slopeor a constant linearity at all times and may even undergo DC levelshifts without affecting the duty cycle d of the output signal 22 of thecomparator 19.

The b divisor signal which is processed through isolation operationalamplifier 56 and applied to the source electrode of a first FET switch96 is modulated in this switch by the negative going pulses 22 which arecoupled through the steering diode 92, and this diode passes only thenegative going pulses 22 to the gate electrode 98 of the N-channel FET96. Thus, the b divisor signal is modulated in the FET 96 and has a dutycycle equal to the duty cycle of the rectangular wave feedback voltage22. This modulated b signal is applied through an input resistor 100 tothe inverting input of the integrating operational amplifier 102 withinthe duty cycle-to-voltage converter stage 26. The noninverting input ofthe op amp 102 is grounded, and the feedback resistor 104 and the inputresistor 100 set the voltage gain of the converter stage 26. Operationalamplifier 102, which also has an integrating feedback capacitor 105,provides the smoothing and filtering action for the chopped signal atthe FET 96 and also provides the desired level of analog feedback signalV,.

The feedback output voltage V, of operational amplifier 102 is equal tok -d-b as set forth in equation (1), and this voltage V; is coupledthrough output resistor 107 into the differential op amp 12 where it iscompared to the analog signal a. The feedback voltage V, continuouslydrives the error voltage e at the output of 'the operational amplifier12 towards zero during variations of the a and b signals, and it is seenfrom equation (4) above that the duty cycle d of the rectangular wavesignal 22 is proportional to a/b and independent of the shape of thetriangular wave clock signal 21.

The feedback signal 22 is also coupled through a steering diode 94 intothe gate of a second FET switch 30 to modulate the multiplier analogsignal 0 which is fed into the source of FET30. The output voltage V onthe drain 106 of the FET 30 is given in equation (5) above, so it isseen that the system embodying the present invention simultaneouslymultiplies the first analog a input signal by the third analog c inputsignal and divides this product by the second analog b input signal.

The V signal on the FET drain 106 is coupled through an input resistor108 to the inverting input of the operational amplifier 110 within theintegrator and low pass filter stage 32. The noninverting input of theoperational amplifier 110 is grounded, and a feedback capacitor 112 anda feedback resistor 114 are connected as shown to the input summingjunction 118 of operational amplifier 110. A variable tap 120 onpotentiometer 124 and the fixed output resistors 122 and 126 areutilized to set the scale factor of the system, and this stage 32filters and smooths the chopped signal coupled from the FET 30 to thesumming junction 118. The gain of the integrator and low pass filterstage 32 is established in accordance with the values of the input andfeedback resistors 108 and 114 and also output resistors 122, 124 and126.

The output node 116 of operational amplifier 110 is coupled through aninput resistor 130 to the noninverting input of the output current andvoltage amplifier 132, and if desired, an additional offset voltage gmay be applied as shown via resistor 138 to the summing junction 134 ofthe amplifier 132. The gain of the amplifier 132 is set in accordancewith the values of feedback resistor 140, and the grounded inputresistor 142 which is connected to the inverting input of the amplifier132.

The amplifier stage 132 may advantageously be constructed with adifferential operational amplifier front end (not shown) and with aDarlington output stage (not shown), and these stages may be connectedin cascade in a well known manner to provide the desired current andvoltage gains for the integrated and filtered signal at node 134. Forimproved stability in the output, it is desirable to provide feedbackvia resistor around both the operational amplifier and Darlington stageswithin the amplifier 132, and the amplifier network 34 has both avoltage output V0 and a current output 10. The output resistor 146 isthe Darlington series output resistor which establishes the relationshipbetween the output current 10 and output voltage V0.

In view of the foregoing, it will be seen that the several objects ofthe invention are achieved and other advantageous results attained.

As various changes could be made in the construction herein describedwithout departing from the scope of the invention, it is intended thatall matter contained in the above description are shown in theaccompanying drawings be interpreted as illustrative rather than in alimiting sense.

e claim:

1. A system for dividing a first or a analog input signal by a second orb analog input signal including, in combination:

a. a closed loop circuit comprising a main signal translating portionand a feedback portion,

b. means in said main signal translating portion for receiving said aanalog input signal,

c. error signal generating means in said main signal translatingportion, connected to said receiving means, for comparing said a analoginput signal with a feedback signal, V,, generated in said feedback loopportion thereby to generate an error signal,

d. means in said main signal translating portion and coupled to saiderror signal generating means for modulating said error signal by aselected waveform to produce a variable duty cycle output signal, and

e. means in said feedback portion for modulating said b analog signal bysaid variable duty cycle output signal for generating said feedbacksignal, V,, whereby said error signal continuously forces V, to equal a,and the variable duty cycle output signal at the output of saidmodulating means has a duty cycle which is proportional to a'lb and issubstantially independent of the precise shape of the waveform utilizedto modulate said error signal.

2. The system defined in claim 1 wherein said error signal generatingmeans includes a differential comparator having one input thereofconnected to receive said a analog input signal and a second inputthereof connected to said feedback portion to receive said feedbacksignal, V,, and to generate an output signal proportional to thedifference between a and V,.

3. The system defined in claim 2 wherein said error signal generatingmeans further includes means connected between said differentialcomparator and said modulating means for integrating said output signalfrom said differential comparator and continuously changing when saidoutput signal is not zero to force V, towards a and force the output ofsaid modulating means to be proportional to a/b.

4. The system defined in claim 1 wherein said modulating means comprisesa voltage-to-duty cycle converter including a differential comparatorconnected to receive said error signal at one input thereof and furtherconnected to a triangular wave generating means, whereby said errorsignal and a triangular wave clock signal from said generating meansdrive said differential comparator between two D.C. levels at a dutycycle proportional to a/b.

5. The system defined in claim 1 wherein said means in said feedbackportion for modulating said b analog signal includes:

a. switch means having an input electrode connected to receive said banalog signal and a control electrode connected to receive said variableduty cycle output signal from said modulating means, whereby said banalog signal is modulated in accordance with the duty cycle of saidoutput signal from said modulating means, and

b. amplifier means interconnecting an output electrode of said switchmeans to an input of said differential comparator thereby to convertsaid modulated b signal to said feedback voltage, V

6. The system defined in claim 5 which further includes a second switchmeans having an input electrode thereof connected to receive a cmultiplying analog signal and having a control electrode connected toreceive said variable duty cycle output signal from said modulatingmeans, whereby the output signal of said second switch means isproportional to a-c/b whereby said system operates to simultaneouslymultiply and divide said a, b and c analog signals.

7. The system defined in claim 3 wherein said modulating means includesa voltage-to-duty cycle converter electrically coupled to the output ofsaid comparing means to generate said variable duty cycle output signalwhich is proportional to the amplitude of said error signal.

8. The system defined in claim 7 herein said voltageto-duty cycleconverter includes a differential comparator for receiving said errorsignal at one input thereof and for receiving a triangular wave clockpulse at the other input thereof for switching the output of said lastnamed differential comparator at a duty cycle proportional to theamplitude of a/b.

9. The system defined in claim 8 wherein said means in said feedbackportion for modulating said b analog signal includes:

a. switch means having an input electrode connected to receive said banalog signal and a control electrode connected to receive said variableduty cycle output signal from said modulating means, whereby said banalog signal is modulated in accordance with the duty cycle of saidoutput signal from said modulating means, and

b. amplifier means interconnecting an output electrode of said switchmeans to an input of said differential comparator thereby to convertsaid modulated b signal to said feedback voltage, V,-.

10. The system defined in claim 9 which further includes a second switchmeans having an input electrode thereof connected to receive a cmultiplying analog signal and having a control electrode connected toreceive said variable duty cycle output signal from said modulatingmeans, hereby the output signal of said second switch means isproportional to a-c/b, and said system operates to simultaneouslymultiply and divide said a,

b and c analog signals.

I l. The system defined in claim 10 wherein said integrating meansincludes an integrator and low pass filter interconnecting the output ofsaid first named differential comparator and one input of said secondnamed differential comparator for integrating the differential outputsignal at the output of said first named comparab. a second isolationamplifier interconnected between the input electrode of said first namedswitch means and a b analog input terminal, and said b analog signalbeing summed at the input of said second isolation amplifier with asecond offset voltage, and

. a third isolation amplifier interconnected between the input electrodeof said second named switch means and a c analog voltage input terminal,hereby said c analog signal may be summed with a third offset voltage atthe input of said third isolation amplifier, whereby the ranges ofcurrents and voltages at the outputs of said output stage may be variedin accordance with said first, second and third offset voltages whichare summed with said a, b and c analog input signals, respectively.

13. The system defined in claim 12 wherein said first and second switchmeans are field-effect transistors each having source, gate and drainelectrodes, with the gate electrodes thereof interconnected throughfirst and second blocking diodes, respectively, to the output of saidvoltage-to-duty cycle converter, whereby said first and second blockingdiodes unidirectionally pass said variable duty cycle output signal tothe respective gate electrodes of said first and second field-effecttransistors to control the signal modulation therein.

14. A system for dividing a first analog signal by a second analogsignal and for multiplying their quotient by a third analog signal, saidsystem including, in combination:

a. means for receiving a first analog signal,

b. means connected to said receiving means for comparing said firstanalog signal with a feedback signal and for generating from thecomparison an error signal which is dependent upon variations in saidfirst analog or feedback signals,

c. first conversion means coupled to said error signal generating meansfor pulse modulating said error signal and producing a variable dutycycle output signal proportional thereto, and

d. feedback means connected to the output of said first conversion meansand including second conversion means connected to receive both saidvariable duty cycle output signal and said second analog signal andresponsive thereto to generate said a feedback signal, whereby saiderror signal continuously forces said feedback signal toward said firstanalog signal toward and forces the duty cycle of the output signal ofsaid first conversion means to be proportional to a/b, and

means for modulating said third analog signal by said variable dutycycle signal to produce an output signal proportional to said quotientmultiplied by said third analog signal.

15. The system defined in claim 14 wherein said error signal generatingmeans includes comparator means connected to both said receiving meansand to said second conversion means for comparing said feedback signaland said first analog signal and for generating an output signalrepresenting the difference between the latter two signals.

16. The system defined in claim 15 wherein a. said error signalgenerating means further includes an integrating amplifier coupled tothe output of said comparator means for providing reset action and acontinuously varying output error signal when said first analog signaland said feedback signal are not equal to zero, said integratingamplifier also providing a high D.C. gain and a high frequency stabilityfor said system and b. said first conversion means includes differentialcomparator means having a first input thereof connected to receive theintegrated error signal from said integrating amplifier and having asecond input thereof connected to receiving a triangular waveform clocksignal, whereby said differential comparator means is switched toprovide a pulse width modulated output signal having a varying dutycycle determined by relative levels of said integrated error signal andsaid triangular waveform clock signal.

17. The system defined in claim 16 wherein said second conversion meansincludes:

a. switching means having one input thereof connected to receive saidvariable duty cycle output signal from said first conversion means andhaving a second input thereof connected to receive said second analogsignal, whereby said second analog signal is modulated in accordancewith the duty cycle of said output signal from said first conversionmeans, and said second conversion means further includes amplifier meansinterconnecting the output of said stitching means to an input of saidcomparator means for continuously driving the signal output voltage ofsaid comparator means towards zero during variations of said first andsecond analog input signals.

18. The system defined in claim 17 wherein said means for modulatingsaid third analog input signal comprises a second switching means havingone input thereof connected to receive said variable duty cycle outputsignal from said first conversion means and a second input thereofconnected to receive a said third analog input signal.

19. The system defined in claim 18 which further includes amplifier andfilter means connected to the output of said second switching means foramplifying and filtering the modulated output signal of said secondswitching means and providing a high gain and the required filtering forthe output of said system.

20. The system defined in claim 19 which further includes an output biasand current driver stage connected to output of said amplifier andfilter means and providing a desired range of output currents andvoltages suitable for driving transducer type final control elements ina process control system.

21. The system defined in claim 20 herein said first and secondswitching means are field-effect transistors. l I I!

1. A system for dividing a first or a analog input signal by a second orb analog input signal including, in combination: a. a closed loopcircuit comprising a main signal translating portion and a feedbackportion, b. means in said main signal translating portion for receivingsaid a analog input signal, c. error signal generating means in saidmain signal translating portion, connected to said receiving means, forcomparing said a analog input signal with a feedback signal, Vf,generated in said feedback loop portion thereby to generate an errorsignal, d. means in said main signal translating portion and coupled tosaid error signal generating means for modulating said error signal by aselected waveform to produce a variable duty cycle output signal, and e.means in said feedback portion for modulating said b analog signal bysaid variable duty cycle output signal for generating said feedbacksignal, Vf, whereby said error signal continuously forces Vf to equal a,and the variable duty cycle output signal at the output of saidmodulating means has a duty cycle which is proportional to a/b and issubstantially independent of the precise shape of the waveform utilizedto modulate said error signal.
 2. The system defined in claim 1 whereinsaid error signal generating means includes a differential comparatorhaving one input thereof connected to receive said a analog input signaland a second input thereof connected to said feedback portion to receivesaid feedback signal, Vf, and to generate an output signal proportionalto the difference between a and Vf.
 3. The system defined in claim 2wherein said error signal generating means furtHer includes meansconnected between said differential comparator and said modulating meansfor integrating said output signal from said differential comparator andcontinuously changing when said output signal is not zero to force Vftowards a and force the output of said modulating means to beproportional to a/b.
 4. The system defined in claim 1 wherein saidmodulating means comprises a voltage-to-duty cycle converter including adifferential comparator connected to receive said error signal at oneinput thereof and further connected to a triangular wave generatingmeans, whereby said error signal and a triangular wave clock signal fromsaid generating means drive said differential comparator between twoD.C. levels at a duty cycle proportional to a/b.
 5. The system definedin claim 1 wherein said means in said feedback portion for modulatingsaid b analog signal includes: a. switch means having an input electrodeconnected to receive said b analog signal and a control electrodeconnected to receive said variable duty cycle output signal from saidmodulating means, whereby said b analog signal is modulated inaccordance with the duty cycle of said output signal from saidmodulating means, and b. amplifier means interconnecting an outputelectrode of said switch means to an input of said differentialcomparator thereby to convert said modulated b signal to said feedbackvoltage, Vf.
 6. The system defined in claim 5 which further includes asecond switch means having an input electrode thereof connected toreceive a c multiplying analog signal and having a control electrodeconnected to receive said variable duty cycle output signal from saidmodulating means, whereby the output signal of said second switch meansis proportional to a.c/b , whereby said system operates tosimultaneously multiply and divide said a, b and c analog signals. 7.The system defined in claim 3 wherein said modulating means includes avoltage-to-duty cycle converter electrically coupled to the output ofsaid comparing means to generate said variable duty cycle output signalwhich is proportional to the amplitude of said error signal.
 8. Thesystem defined in claim 7 herein said voltage-to-duty cycle converterincludes a differential comparator for receiving said error signal atone input thereof and for receiving a triangular wave clock pulse at theother input thereof for switching the output of said last nameddifferential comparator at a duty cycle proportional to the amplitude ofa/b.
 9. The system defined in claim 8 wherein said means in saidfeedback portion for modulating said b analog signal includes: a. switchmeans having an input electrode connected to receive said b analogsignal and a control electrode connected to receive said variable dutycycle output signal from said modulating means, whereby said b analogsignal is modulated in accordance with the duty cycle of said outputsignal from said modulating means, and b. amplifier meansinterconnecting an output electrode of said switch means to an input ofsaid differential comparator thereby to convert said modulated b signalto said feedback voltage, Vf.
 10. The system defined in claim 9 whichfurther includes a second switch means having an input electrode thereofconnected to receive a c multiplying analog signal and having a controlelectrode connected to receive said variable duty cycle output signalfrom said modulating means, hereby the output signal of said secondswitch means is proportional to a.c/b, and said system operates tosimultaneously multiply and divide said a, b and c analog signals. 11.The system defined in claim 10 wherein said integrating means includesan integrator and low pass filter interconnecting the output of saidfirst named differential comparator and one input of said second nameddifferential comparator foR integrating the differential output signalat the output of said first named comparator and providing reset actionin the generation of said error signal, said integrator and low passfilter further providing a high DC gain and a high frequency stabilityfor said system.
 12. The system defined in claim 11 which furtherincludes: a. a first input isolation amplifier connected between saidfirst named differential comparator and an a analog input voltageterminal for summing said a analog input voltage with a first offsetvoltage, b. a second isolation amplifier interconnected between theinput electrode of said first named switch means and a b analog inputterminal, and said b analog signal being summed at the input of saidsecond isolation amplifier with a second offset voltage, and c. a thirdisolation amplifier interconnected between the input electrode of saidsecond named switch means and a c analog voltage input terminal, herebysaid c analog signal may be summed with a third offset voltage at theinput of said third isolation amplifier, whereby the ranges of currentsand voltages at the outputs of said output stage may be varied inaccordance with said first, second and third offset voltages which aresummed with said a, b and c analog input signals, respectively.
 13. Thesystem defined in claim 12 wherein said first and second switch meansare field-effect transistors each having source, gate and drainelectrodes, with the gate electrodes thereof interconnected throughfirst and second blocking diodes, respectively, to the output of saidvoltage-to-duty cycle converter, whereby said first and second blockingdiodes unidirectionally pass said variable duty cycle output signal tothe respective gate electrodes of said first and second field-effecttransistors to control the signal modulation therein.
 14. A system fordividing a first analog signal by a second analog signal and formultiplying their quotient by a third analog signal, said systemincluding, in combination: a. means for receiving a first analog signal,b. means connected to said receiving means for comparing said firstanalog signal with a feedback signal and for generating from thecomparison an error signal which is dependent upon variations in saidfirst analog or feedback signals, c. first conversion means coupled tosaid error signal generating means for pulse modulating said errorsignal and producing a variable duty cycle output signal proportionalthereto, and d. feedback means connected to the output of said firstconversion means and including second conversion means connected toreceive both said variable duty cycle output signal and said secondanalog signal and responsive thereto to generate said a feedback signal,whereby said error signal continuously forces said feedback signaltoward said first analog signal toward and forces the duty cycle of theoutput signal of said first conversion means to be proportional to a/b,and e. means for modulating said third analog signal by said variableduty cycle signal to produce an output signal proportional to saidquotient multiplied by said third analog signal.
 15. The system definedin claim 14 wherein said error signal generating means includescomparator means connected to both said receiving means and to saidsecond conversion means for comparing said feedback signal and saidfirst analog signal and for generating an output signal representing thedifference between the latter two signals.
 16. The system defined inclaim 15 wherein a. said error signal generating means further includesan integrating amplifier coupled to the output of said comparator meansfor providing reset action and a continuously varying output errorsignal when said first analog signal and said feedback signal are notequal to zero, said integrating amplifier also providing a high D.C.gain and a high frequency stability for said system and b. said firstconVersion means includes differential comparator means having a firstinput thereof connected to receive the integrated error signal from saidintegrating amplifier and having a second input thereof connected toreceiving a triangular waveform clock signal, whereby said differentialcomparator means is switched to provide a pulse width modulated outputsignal having a varying duty cycle determined by relative levels of saidintegrated error signal and said triangular waveform clock signal. 17.The system defined in claim 16 wherein said second conversion meansincludes: a. switching means having one input thereof connected toreceive said variable duty cycle output signal from said firstconversion means and having a second input thereof connected to receivesaid second analog signal, whereby said second analog signal ismodulated in accordance with the duty cycle of said output signal fromsaid first conversion means, and b. said second conversion means furtherincludes amplifier means interconnecting the output of said stitchingmeans to an input of said comparator means for continuously driving thesignal output voltage of said comparator means towards zero duringvariations of said first and second analog input signals.
 18. The systemdefined in claim 17 wherein said means for modulating said third analoginput signal comprises a second switching means having one input thereofconnected to receive said variable duty cycle output signal from saidfirst conversion means and a second input thereof connected to receive asaid third analog input signal.
 19. The system defined in claim 18 whichfurther includes amplifier and filter means connected to the output ofsaid second switching means for amplifying and filtering the modulatedoutput signal of said second switching means and providing a high gainand the required filtering for the output of said system.
 20. The systemdefined in claim 19 which further includes an output bias and currentdriver stage connected to output of said amplifier and filter means andproviding a desired range of output currents and voltages suitable fordriving transducer type final control elements in a process controlsystem.
 21. The system defined in claim 20 herein said first and secondswitching means are field-effect transistors.